instruction execution
英 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]
美 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]
网络 指令执行
英英释义
noun
- (computer science) the process of carrying out an instruction by a computer
双语例句
- Static instruction scheduling decides the execution order of instructions and improves the instruction-level parallelism by reducing stall caused by dependences.
静态指令调度决定指令执行顺序，屏蔽指令间由于依赖关系而产生的延迟，从而提高了指令的并行度。 - It is more efficient to design a simple instruction set that enable the execution of one instruction per clock cycle.
设计一个能够在一个时钟周期执行一条指令的简单指令系统才是更有效的。 - The article essentially describes such points as instruction execution and memory management in constructing a virtual running embedded system.
文中着重介绍了构建嵌入式虚拟运行平台中的指令执行、存储器管理等核心技术问题。 - Characteristics of the microprocessor are fast speed and nimble instructions. The way of raising speed is to adopt pipelining in instruction execution.
它的运算速度提高的途径是指令的执行采用流水线方式，指令缓冲部件IB采用两个体交替接收指令和执行指令的办法来减少取指令的等待时间。 - Traditional programming model like C, C++ and Fortran are poorly suited to multi-core architectures because of the assumed single instruction stream execution model and centralized memory structure.
C、C++和Fortran等基于单指令流和统一存储结构的传统编程模型已经无法适应多核处理器结构。 - Propose the run time dispatched instruction decoder and issue logic based on instruction execution cycle.
提出基于指令类型动态分配的译码器设计方案和基于指令执行周期的动态逻辑发射方案。 - In the traditional Cache, the Cache hit ratio is insured only by the address locality of memory reference instruction stream during program execution, it restricts the improvement of Cache hit ratio.
在传统的Cache中，仅仅依靠程序执行时访存指令流地址的局域性来保证较高的Cache命中率，使得Cache命中率的提高受到限制。 - Compile the assembler into machine code so that generate PLE file in order to implement the execution mechanism of PLC virtual machine. In this way, the instruction execution speed of PLC is greatly increased and we can save much memory.
用汇编编译器编译转变成功的汇编程序产生机器码，从而构造出可执行文件&PLE文件，实现PLC虚拟机的机器码执行机制，这样大大提高了PLC指令的执行速度，同时大大节约了内存空间。 - This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture, issuing multiple instructions in one machine cycle. Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed.
本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系，并分析了新型超标量RISC结构的实现方案，其中包括具有单个执行部件和多个执行部件的结构。 - As the core of SOC, CPU ′ s performance is mostly determined by instruction ′ s execution efficiency. Pipeline increases the instruction ′ s execution pace and improves the CPU ′ s performance.
作为SOC的核心，CPU的性能主要取决于指令的执行效率，而采用流水线方式大大增加了指令的执行速度，提高了CPU的性能。