instruction execution

英 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

美 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

网络  指令执行

计算机

英英释义

noun

• (computer science) the process of carrying out an instruction by a computer
  Synonym:execution

双语例句

• A technique whereby the receiver fetches the next instruction before completing execution of the previous instruction, in order to increase processing speed.
  在前一条指令全部执行完之前就开始取下一条指令，以提高处理速度的一种技术。
• The article essentially describes such points as instruction execution and memory management in constructing a virtual running embedded system.
  文中着重介绍了构建嵌入式虚拟运行平台中的指令执行、存储器管理等核心技术问题。
• If supervision engineer issued a directive, contractor should change by supervision engineer change instruction execution.
  若监理工程师发出了变更指令，承包人就应按监理工程师的变更指令执行。
• Pipeline is dealing with instruction, including instruction decode, issue, and execution.
  流水线正在处理指令，包括指令解码、发布和执行。
• This article probes into a kind of encryption method for files, which is different from the usual way. It also studies the encryption method for instruction inverse execution, which means how to use inverse instruction stream to realize the file encryption.
  研究一种打破常规的文件加密方法，指令的逆运动加密方法，即如何采用逆指令流来实现对计算机文件的加密。
• Traditional programming model like C, C++ and Fortran are poorly suited to multi-core architectures because of the assumed single instruction stream execution model and centralized memory structure.
  C、C++和Fortran等基于单指令流和统一存储结构的传统编程模型已经无法适应多核处理器结构。
• Compile the assembler into machine code so that generate PLE file in order to implement the execution mechanism of PLC virtual machine. In this way, the instruction execution speed of PLC is greatly increased and we can save much memory.
  用汇编编译器编译转变成功的汇编程序产生机器码，从而构造出可执行文件&PLE文件，实现PLC虚拟机的机器码执行机制，这样大大提高了PLC指令的执行速度，同时大大节约了内存空间。
• Bochs was developed purely in the C++ language for interpreted x86 instruction execution and platform emulation.
  对于解译的x86指令执行和平台仿真，Bochs完全是用C++语言开发的。
• In the traditional Cache, the Cache hit ratio is insured only by the address locality of memory reference instruction stream during program execution, it restricts the improvement of Cache hit ratio.
  在传统的Cache中，仅仅依靠程序执行时访存指令流地址的局域性来保证较高的Cache命中率，使得Cache命中率的提高受到限制。
• This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture, issuing multiple instructions in one machine cycle. Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed.
  本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系，并分析了新型超标量RISC结构的实现方案，其中包括具有单个执行部件和多个执行部件的结构。